`timescale 1ns/1ns
module adder1_test;
wire sum,cout;
reg a,b,cin;
adder1 u1(a,b,cin,cout,sum);
initial
  begin
    a=0;b=0;cin=0;
    #20 a=1;b=1;cin=0;
    #20 a=1;b=0;cin=0;
    #20 a=1;b=1;cin=1;
    #20 a=0;b=1;cin=1;
    #20 a=1;b=1;cin=0;
    #20 $stop;
end
initial $monitor($time, , ,"a=%b b=%b cin=%b sum=%b cout=%b",a,b,cin,sum,cout);
endmodule